A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique

AUTHOR(S):

Paanshul Dobriyal, Karna Sharma, Manan Sethi, Geetanjali Sharma

TITLE

A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique

PDF

KEYWORDS

flip-flop; low power integrated circuit; power delay product; MTCMOS

ABSTRACT

Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in International technology roadmap for semiconductors. In any integrated circuit, clock distribution network and flip -flop consumes large amount of power as they make maximum number of internal transitions. In this paper, various techniques for implementing flip–flops with low power clocking system are analyzed. Among those techniques clocked pair shared flip-flop (CPSFF) consume least power than conditional data mapping flip flop (CDMFF), conditional discharge flip flop (CDFF) and conventional double edge triggered flip-flop(DEFF). We propose a novel CPSFF using Multi-Threshold voltage CMOS (MTCMOS) technique which reduces the power consumption by approximately 20% to 70% than the original CPSFF. In addition, to build a clocking system, double edge triggering and low swing clocking can be easily incorporated into the new flip-flop.

REFERENCES

[1] M. Pedram, “Power minimization in IC Design: Principles and applications,” ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp.3-56, Jan. 1996.

[2] Z. Peiyi, M. Jason, K. Weidong, W. Nan, and W. Zhongfeng “Design of Sequential Elements for Low Power Clocking System” IEEE Transaction of Very large Scale Integration “July 2010.

[3] A. Keshavarzi, K. Roy, and C. F. Hawkins, “Intrinsic leakage in low power deep submicron CMOS ICs,” in Proc. Int. Test Conf., pp. 146– 155, 1997.

[4] S.M. Kang, Y. Leblebici “CMOS Digital Integrated Circuits analysis and design” third edition, TMH, 2003.

[5] N.Weste and D. Harris, “CMOS VLSI Design”. Reading, MA: Addison Wesley, 2004.

[6] M. Pedram, Q. Wu,and X. Wu, “A New Design for Double Edge Triggered Flip-flops”, in Jan.2002.

[7] P. Zhao, T. K. Darwish, and M. A. Bayoumi, “High-Performance and Low-Power Conditional Discharge Flip-Flop”, IEEE transactions on very large scale integration (VLSI) systems, vol.12 no.5, May 2004.

[8] T.Kavitha , Dr.V.Sumalatha “A New Reduced Clock Power Flipflop for Future SOC Applications ”. International Journal of Computer Trends and Technology, volume 3 Issue 4, 2012.

[9] C. K. Teh, M. Hamada, T. Fujita,H. Hara, N. Ikumi, and Y. Oowaki, “Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems”. IEEE Transactions on very large scale integration (VLSI) systems, vol. 14, no. 12,December 2006

[10] F. Mohammad, L. A. Abhilas and P. Srinivas “A new parallel counter architecture with reduced transistor count for power and area optimization”, International conference on Electrical and Electronics Engineering, Sept., 2012.

[11] Bhuvana S, Sangeetha R “A Survey on Sequential Elements for Low Power Clocking System”,Journal of Computer Applications ISSN: 0974 – 1925,Volume-5, Issue EICA2012-3, February 10, 2012.

[12] B. Kousalya, “Low Power Sequential Elements for Multimedia and Wireless Communication applications”, July 2012 [13] Mutoh S et al, “1-V Power supply high-speed digital circuit technology with multithreshold- voltage CMOS”, IEEE J. Solid State Circuits, Vol. 30, pp. 847-854, August 1995.

[14] Hemantha S,Dhawan A and Kar H ,“Multi-threshold CMOS design for low power digital circuits”,TENCON 2008-2008 IEEE Region 10 Conference,pp.1-5,2008.

[15] Q. Zhou, X.Zhao, Y.Cai, X.Hong, “An MTCMOS technology for low-power physical design”, Integration VLSI J. (2008)

Cite this paper

Paanshul Dobriyal, Karna Sharma, Manan Sethi, Geetanjali Sharma. (2016) A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique. International Journal of Circuits and Electronics, 1, 33-38