Performance Evaluation of a Network-on-Chip Interconnect Architecture Based on Nanoelectronic Devices

AUTHOR(S):

Edylara Ribeiro Rangel, Janaina Gonçalves Guimarães

TITLE

Performance Evaluation of a Network-on-Chip Interconnect Architecture Based on Nanoelectronic Devices

ABSTRACT

In this work, a performance evaluation concerning energy consumption of a nanoelectronic Network-on-Chip (NoC) architecture considering interconnect effects will be presented. The goal is to determine the interconnection influence upon the NoC architecture, in a nanoelectronic system. For power consumption calculations it was used a nanoelectronic router based on single-electron transistors (SET). In this router the building block for designing all digital modules were a NAND gate. The mesh topology will be adopted, since most NoCs uses this network topology for regularity and modularity. Also, an analytic model for energy consumption in NoCs will be adopted. Finally, a short comparison between MOS and SET performances will be shown to reinforce the important role that nanoelectronic can offer for this type of architecture in the future.

KEYWORDS

nanoelectronic, Network-on-Chip (NoC), interconnect, power consumption, carbon nanotubes (CNT), single-electron transistor (SET)

REFERENCES

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Cite this paper

Edylara Ribeiro Rangel, Janaina Gonçalves Guimarães. (2017) Performance Evaluation of a Network-on-Chip Interconnect Architecture Based on Nanoelectronic Devices. International Journal of Mathematical and Computational Methods, 2, 231-234