Comparison of D Flip-Flops Using Variability and Delay Analysis for Sigma Delta ADC

AUTHOR(S):

TITLE

Comparison of D Flip-Flops Using Variability and Delay Analysis for Sigma Delta ADC

ABSTRACT

Circuit with better robustness and minimum transistors is always preferred in a market to design a smart chip. Speed and variability of D flip-flop are required in sigma delta ADC to count the number of pulses after comparator. The paper aims to design single phase clocked feedback D flip-flop to achieve variability and delay by using minimum transistors. Instead of pass gate, the proposed circuit consists of feedback path isolation with inversion to lessen a number of transistors. It is compared with different kinds of D flip-flops that are used in sequential circuits. In this work, it is found that speed is better than Push pull isolation D flip-flop and robustness is quite good by minimum transistor. Circuit layout is built in Electric VLSI Cad Tool. Supply voltage of 0.9 V and 180nm technology is used.

KEYWORDS

D Flip-Flop, Delay, Variability, Speed, Robustness, Transistor

REFERENCES

[1] Himanshu Kumar, Amresh Kumar, Aminul Islam, Comparative Analysis of D Flip-Flops in Terms of Delay and its Variability, 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) IEEE, 2015.

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[4] J. Mahattanakul, Design Procedure for Two-Stage CMOS Operational Amplifiers Employing Current Buffer, IEEE Transactions On Circuits And Systems—Ii: Express Briefs, Vol. 52, No. 11, November 2005.

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Cite this paper

Yogita Gajare, Arti Khaparde. (2018) Comparison of D Flip-Flops Using Variability and Delay Analysis for Sigma Delta ADC. International Journal of Circuits and Electronics, 3, 7-13