Comparison of D Flip-Flops Using Variability and Delay Analysis for Sigma Delta ADC

Abstract: Circuit with better robustness and minimum transistors is always preferred in a market to design a smart chip. Speed and variability of D flip-flop are required in sigma delta ADC to count the number of pulses after comparator. The paper aims to design single phase clocked feedback D flip-flop to achieve variability and delay by using minimum transistors. Instead of pass gate, the proposed circuit consists of feedback path isolation with inversion to lessen a number of transistors. It is compared with different kinds of D flip-flops that are used in sequential circuits. In this work, it is found that speed is better than Push pull isolation D flip-flop and robustness is quite good by minimum transistor. Circuit layout is built in Electric VLSI Cad Tool. Supply voltage of 0.9 V and 180nm technology is used.